Propagation Functions for Logic Errors and Events

We study the problem of fault propagation, which is a very important and time consuming task performed by an ATPG tool, and develop a generic framework that supports generation of propagation functions per circuit line for both logic and timing faults. The proposed methodology is an alternative to the traditional function-based ATPG techniques for logic errors (such as stuck-at faults), but can also be used under timing (delay) fault models where event propagation is required. We show that the propagation functions for all circuit lines can be generated using a single topological traversal of a modified circuit (the circuit modification is linear to the original circuit depth). Various function representation environments (BDDs, BEDs, and BNETs) are examined, and experimental results on the ISCAS’85 and ISCAS’89 are presented. In addition, our experiments demonstrate that this more generic framework compares very similar to the traditional boolean difference formulation for logic error propagation functions.